1 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 description integrated programmable clock divider and 1:2 fanout buffer guaranteed ac performance over temperature and voltage: > 2.5ghz f max < 250ps t r /t f < 15ps within device skew low jitter design: < 10ps pp total jitter < 1ps rms cycle-to-cycle jitter unique input termination and v t pin for dc-coupled and ac-coupled inputs; cml, pecl, lvds and hstl ttl/cmos inputs for select and reset 100k ep compatible lvpecl outputs parallel programming capability programmable divider ratios of 1, 2, 4, 8 and 16 low voltage operation 2.5v or 3.3v output disable function ?0 c to 85 c temperature range available in 16-pin (3mm x 3mm) mlf package features 2.5ghz any diff. in-to-lvpecl programmable clock divider/ fanout buffer with internal termination precision edge sy89874u applications sonet/sdh line cards transponders high-end, multiprocessor sensors rev.: f amendment: /0 issue date: march 2008 this low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622mhz or higher) cml, lvpecl, lvds or hstl clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency- locked, lower speed version of the input clock. available divider ratios are 2, 4, 8 and 16, or straight pass-through. in a typical 622mhz clock system this would provide availability of 311mhz, 155mhz, 77mhz or 38mhz auxiliary clock components. the differential input buffer has a unique internal termination design that allows access to the termination network through a v t pin. this feature allows the device to easily interface to different logic standards. a v ref-ac reference is included for ac-coupled applications. the /reset input asynchronously resets the divider. in the pass-through function (divide by 1) the /reset synchronously enables or disables the outputs on the next falling edge of in (rising edge of /n). functional block diagram typical performance precision edge is a registered trademark of micrel, inc. micro leadframe and mlf are trademarks of amkor technology, inc. in /in s0 s1 q1 /q1 q0 /q0 r0 r1 /reset v t v ref-ac s2 divided by 2, 4, 8 or 16 enable mux mux enable ff decoder divide-by-4 lvds 622mhz clock in oc-12 to oc-3 translator/divider lvpecl 155.5mhz clock out 622mhz in /q0 q0 /in in 155.5mhz out precision edge
2 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 package/ordering information pin number pin name pin function 12, 9 in, /in differential input: internal 50 ? termination resistors to v t input. flexible input accepts any differential input. see ?nput interface applications?section. 1, 2, 3, 4 q0, /q0 differential buffered lvpecl outputs: divided by 1, 2, 4, 8 or 16. see ?ruth table. q1, /q1 unused pecl outputs may be left floating with no impact on jitter performance. 16, 15, 5 s0, s1, s2 select pins: see ?ruth table.?lvttl/cmos logic levels. internal 25k ? pull-up resistor. logic high if left unconnected (divided by 16 mode.) input threshold is v cc /2. 6 nc no connect. 8 /reset lvttl/cmos logic levels: internal 25k ? pull-up resistor. logic high if left unconnected. /disable apply low to reset the divider (divided by 2, 4, 8 or 16 mode). also acts as a synchronous disable/enable function. the reset and disable function occurs on the next high-to-low clock input transition. input threshold is v cc /2. 10 vref-ac reference voltage: equal to v cc ?.4v (approx.). used for ac-coupled applications only. decouple the v ref-ac pin with a 0.01 f capacitor. see ?nput interface applications?section. 11 vt termination center-tap: for cml or lvds inputs, leave this pin floating. otherwise, see figures 2a to 2f ?nput interface applications?section. 7, 14 vcc positive power supply: bypass with 0.1 f//0.01 f low esr capacitor. 13 gnd ground. pin description 13 14 15 16 12 11 10 9 1 2 3 4 8 7 6 5 q0 / q0 q1 / q1 in vt vref-ac /in s0 s1 vcc gnd s2 nc vcc / reset 16-pin mlf (mlf-16) /reset (1) s2 s1 s0 outputs 1 0 x x reference clock (pass through) 1 1 0 0 reference clock 2 1 1 0 1 reference clock 4 1 1 1 0 reference clock 8 1 1 1 1 reference clock 16 0 (1) 1 x x q = low, /q = high clock disable note 1. reset/disable function is asserted on the next clock input (in, /in) high-to-low transition. truth table ordering information (1) package operating package lead part number type range marking finish sy89874umi mlf-16 industrial 874u sn-pb SY89874UMITR (2) mlf-16 industrial 874u sn-pb sy89874umg (3) mlf-16 industrial 874u with nipdau pb-free bar line indicator pb-free sy89874umgtr (2, 3) mlf-16 industrial 874u with nipdau pb-free bar line indicator pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs.
3 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 note 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operati on is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximu m ratlng conditions for extended periods may affect device reliability. note 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. note 3. due to the limited drive capability use for input of the same package only. note 4. junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device s most negative potential on the pcb. absolute maximum ratings (note 1) supply voltage (v cc ) .................................. 0.5v to +4.0v input voltage (v in ) .................................. 0.5v to v cc +0.3 ecl output current (i out ) continuous ......................................................... 50ma surge ................................................................ 100ma input current in, /in (i in ) .......................................... 50ma v t current (i vt ) ...................................................... 100ma v ref-ac sink/source current (i vref-ac ), note 3 ....... 2ma lead temperature (soldering 20 sec.) ...................... 260 c storage temperature (t s ) ....................... 65 c to +150 c operating ratings (note 2) supply voltage (v cc ) ................ +3.3v 10% or +2.5v 5% ambient temperature (t a ) ......................... 40 c to +85 c package thermal resistance mlf ( ja ) still-air ............................................................. 60 c/w 500lfpm ............................................................ 54 c/w mlf ( jb ), note 4 junction-to-board ............................................ 32 c/w t a = 40 c to +85 c; unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 3.63 v i cc power supply current no load, max. v cc 50 75 ma r in differential input resistance 90 100 110 ? (in-to-/in) v ih input high voltage (in, /in) note 3 0.1 v cc +0.3 v v il input low voltage (in, /in) note 3 0.3 v ih 0.1 v v in input voltage swing notes 3, 4 0.1 v cc v v diff_in differential input voltage swing notes 3, 4, 5 0.2 v |i in | input current (in, /in) note 3 45 ma v ref-ac reference voltage note 6 v cc 1.525 v cc 1.425 v cc 1.325 v note 1. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. note 2. specification for packaged product only. note 3. due to the internal termination (see input structures ) the input current depends on the applied voltages at in, /in and v t inputs. do not apply a combination of voltages that causes the input current to exceed the maximum limit! note 4. see timing diagram for v in definition. v in (max) is specified when v t is floating. note 5. see typical operating characteristics section for v diff definition. note 6. operating using v in is limited to ac-coupled pecl or cml applications only. connect directly to v t pin. dc electrical characteristics (notes 1, 2) v cc = 3.3v 10% or 2.5v 5%; t a = 40 c to +85 c, r l = 50 ? to v cc 2v; unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage v cc 1.145 v cc 1.020 v cc 0.895 v v ol output low voltage v cc 1.945 v cc 1.820 v cc 1.695 v v out output voltage swing 550 800 1050 mv v diff_out differential output voltage swing 1.10 1.60 2.10 v note 1. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. note 2. specification for packaged product only. (100kep) lvpecl dc electrical characteristics (notes 1, 2)
4 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 v cc = 3.3v 10% or 2.5v 5%; t a = 40 c to +85 c; unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current 125 20 a i il input low current 300 a note 1. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. note 2. specification for packaged product only. lvttl/cmos dc electrical characteristics (notes 1, 2)
5 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 v cc = 3.3v 10% or 2.5v 5%; t a = 40 c to +85 c; unless otherwise stated. symbol parameter condition min typ max units f max maximum output toggle frequency output swing 400mv 2.5 ghz maximum input frequency divide by 2, 4, 8, 16 3.2 ghz t pd differential propagation delay input swing < 400mv 540 650 790 ps in to q input swing 400mv 480 600 730 ps t skew within-device skew (diff.) note 3 715 ps q0 q1 part-to-part skew (diff.) note 3 250 ps t rr reset recovery time note 4 600 ps t jitter cycle-to-cycle jitter note 5 1ps rms total jitter note 6 10 ps pp t r ,t f rise/fall time (20% to 80%) 70 150 250 ps note 1. measured with 400mv input signal, 50% duty cycle, all outputs loaded with 50 ? to v cc 2v, unless otherwise stated. note 2. specification for packaged product only. note 3. skew is measured between outputs under identical transitions. note 4. see timing diagram. note 5. cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. t jitter_cc =t n t n+1 , where t is the time between rising edges of the output signal. note 6. total jitter definition: with an ideal clock input, of frequency f max (device), no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. ac electrical characteristics (notes 1, 2) timing diagram v in /reset in /in /q q t pd t rr v cc/2 v in swing v out swing
6 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 3.3v, v in = 400mv, t a = 25 c, unless otherwise stated. 0 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 qa amplitude (mv) frequency (mhz) qa output amplitude vs. frequency 0 100 200 300 400 500 600 700 800 900 0 200 400 600 800 1000 1200 propagation delay (ps) input swing (mv) in to q propagation delay vs. input swing 400 500 600 700 800 -40 -20 0 20 40 60 80 100 120 propagation delay (ps) temperature ( c) in to q propagation delay vs. temperature 622mhz output time (200ps/div.) output swing (100mv/div.) /q q 1.25ghz output time (200ps/div.) output swing (100mv/div.) /q q 2.5ghz output time (100ps/div.) output swing (100mv/div.) /q q
7 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 input buffer structure v cc gnd 50 ? 50 ? in v t /in 1.86k ? 1.86k ? 1.86k ? 1.86k ? figure 2a. simplified differential input buffer v cc gnd s0 s1 s2 /reset r 25k ? r figure 2b. simplified ttl/cmos input buffer definition of single-ended and differential swing v in, v out 800mv (typical) 1600mv (typical) v diff_in , v diff_out figure 1a. single-ended swing figure 1b. differential swing
8 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 input interface applications cml in /in v t nc gnd sy89874u v cc v cc v ref-ac nc figure 3a. dc-coupled cml input interface cml in /in v t gnd sy89874u v cc v cc v ref-ac v cc 0.01 f figure 3b. ac-coupled cml input interface pecl in /in vt gnd sy89874u v cc v cc v ref-ac nc 50 ? * bypass with 0.01f to v cc 0.01f v cc 2v* v cc figure 3c. dc-coupled pecl input interface pecl in /in v t gnd sy89874u v cc r pd * *note. 3.3v = r pd = 100 ? 2.5v = r pd = 50 ? r pd * v cc gnd v ref-ac v cc 0.01 f figure 3d. ac-coupled pecl input interface lv d s in /in v t nc gnd sy89874u v cc v cc v ref-ac nc figure 3e. lvds input interface hstl in /in v t gnd sy89874u v cc v cc gnd nc v ref-ac figure 3f. hstl input interface part number function data sheet link sy89871u 2.5ghz any diff. in-to-lvpecl http://www.micrel.com/product-info/products/sy89871u.shtml programmable clock divider/fanout buffer w/internal termination mlf application note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf hbw solutions new products and applications http://www.micrel.com/product-info/products/solutions.shtml related product and support documentation
9 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 lvpecl output termination recommendations r2 82 ? r2 82 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc 2v r1 130 ? r1 130 ? +3.3v figure 4a. parallel termination thevenin equivalent note 1. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ? z = 50 ? z = 50 ? 50 ? 50 ? 50 ? +3.3v +3.3v source destination r b (optional) c1 0.01 f figure 4b. three-resistor y termination note 1. power-saving alternative to thevenin termination. note 2. place termination resistors as close to destination inputs as possible. note 3. r b resistor sets the dc bias voltage, equal to v t . for +3.3v systems r b = 46 ? to 50 ? . for +2.5v systems r b = 39 ? note 4. c1 is an optional bypass capacitor intended to compensate for any t r /t f mismatches. +3.3v +3.3v z o = 50 ? r2 82 ? +3.3v +3.3v r1 130 ? r1 130 ? r2 82 ? v t = v cc 2v q /q r3 1k ? r4 1.6k ? v t = v cc 1.3v figure 4d. terminating unused i/o note 1. unused output (/q) must be terminated to balance the output. note 2. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ? , r3 = 1.25k ? , r4 = 1.2k ? .
10 precision edge sy89874u micrel, inc. m9999-031208 hbwhelp@micrel.com or (408) 955-1690 package ep- exposed pad die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 16-pin mlf package (always solder, or equivalent, the exposed pad to the pcb) 16-pin micro leadframe (mlf-16) package notes: note 1. package meets level 2 moisture sensitivity classification, and is shipped in dry-pack form. note 2. exposed pads must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is as sumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.
|
